Traditional test systems used for WLR, PCM, and Die-Sort do not have the measurement dynamic range or resolution to meet the new efficiency requirements (higher voltage, lower leakage current, lower on-resistance), or they require time-consuming manual reconfiguration to switch between low- and high-voltage tests. To meet your fab’s productivity goals, you can no longer afford to manually switch between two separate test systems for low voltage and high voltage semiconductor testing. Only Keithley can perform fully automatic wafer-level tests up to 3kV in a single probe touchdown.
Perform all high- and low-voltage tests in a single pass without changing equipment or test setup. Get full 3kV sourcing capability combined with sub-pA measurement resolution, which eliminates the need to re-configure the test setup or use two separate test systems when moving from high voltage to low voltage breakdown tests. Minimize connectivity issues due to manual cabling and probing. Reduce false failures by ensuring high quality measurements. Safely rely on test results to adjust manufacturing process parameters to maximize yields.
Automate all Capacitance tests, including complex 3-terminal measurements. Fully automate 2- or 3-terminal transistor capacitance measurements to quickly evaluate switching characteristics such as speed, energy, and charge with Keithley’s high voltage switching matrix.
Minimize test times, maximize test throughput and reduce cost of test with Keithley’s Test Script Processing (TSP) technology and virtual backplane (TSP-Link) that enables high-speed triggering, timing, and synchronization between all elements of the system.
Application note |
Application note |
This application note explores several measurement techniques and approaches that enable automated HV wafer level characterization on multiple pins without sacrificing low voltage performance or throughput, as well as share results and experiences in the emerging field of HV wafer-level testing. |
This application note explores several measurement techniques and approaches that enable automated HV wafer level characterization on multiple pins without sacrificing low voltage performance or throughput, as well as share results and experiences in the emerging field of HV wafer-level testing. |