Accurate, Repeatable PCIe Measurements

The recently launched PCIe 6.0 Base specification doubles bandwidth and power efficiency. PCIe 6.0 introduces features such as PAM4 signaling and forward error correction (FEC) to support these high data transfer rates (64.0 GT/s) while maintaining low latency. Tektronix's PCIe 6.0 transmitter (Tx) and receiver (Rx) test solutions enable engineers to address the latest design and validation problems. Intuitive tools provide out-of-the-box support for measurements like signal-to-noise distortion ratio (SNDR) and uncorrelated jitter as well as receiver stressed eye TP3/TP2 calibration and Instrument noise compensation mandated by the latest specifications.

Our PCIe transmitter test solutions maintain backward compatibility by offering PCIe transmitter validation and compliance solutions from 2.5 GT/s to 32.0 GT/s ( Gen1 to Gen5). Support spans from early silicon voltage/timing characterization to platform level transmitter and reference clock measurements. Tektronix technology leaders ensure these solutions stay relevant by incorporating all engineering change notices (ECNs) and supporting the PCI-SIG compliance workshops as an approved solution.

PCIe receiver validation is notoriously difficult due to the sensitivity of calibrating the stressed eye signal across a high loss channel. Tektronix’s PCIe receiver test solutions bring confidence that your design was thoroughly tested at the required bit error rate (BER) target. Our intuitive step-by-step tools provide link training routines for the Anritsu MP1900A BERT to ensure your receiver is tested accurately. Automated testing supports stressed eye calibration, the latest transmitter and receiver link equalization compliance tests, custom BER runs, and jitter tolerance characterization. This framework also powers easy transmitter PLL bandwidth and peaking measurements.

The TMT4 Margin Tester provides design and validation engineers with a new tool for diagnosing problems at the PCIe physical layer.  It evaluates the link health of Gen3 and Gen4 PCIe designs dramatically faster, more easily, and more cost effectively, making it possible to identify problems earlier in the development cycle. Simple to set-up and configure, the TMT4 Margin Tester’s targeted Tx/Rx capability quickly captures issues with PCIe Gen 3 and Gen 4 communications on both ends of the link and enables teams to evaluate the link health of up to x16 Gen 4 links, across all PCIe presets 0-9, in minutes.

Datacenter architectures must increasingly respond to data movement and access demands while minimizing power, increasing efficiency, and supporting larger and more diverse applications. Building on the strength of the PCIe physical layer, CXL addresses these requirements allowing processors to access the same memory resources efficiently, to talk together, and to run on a single architecture. Physical layer solutions from Tektronix support the fastest CXL data rate (32 GT/s) and diverse form factors expected from this emerging technology.